1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a method for fabricating a split gate flash memory. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for preventing polymer residue from being formed in a space between the split gate area on both sides of the flash memory device and for enhancing the electrical characteristics of the flash memory device.
2. Discussion of the Related Art
Flash memory technology has been continuously developed by enhancing the cell structure in various ways. Such variety of forms includes the stacked gate cell structure and the split gate cell structure. The stacked gate cell structure is formed of a sequential deposition of a floating gate and a control gate. The stacked gate cell has the problem of over-erasing, which occurs when the floating gate is excessively discharged. A threshold voltage of the excessively discharged cell has a negative (−) value. Accordingly, an electric current flows through even when a cell is not selected. In other words, the current flows when a read voltage is not applied to the control gate. The split gate cell structure has been proposed in order to prevent the problem of over-erasing.
FIG. 1 illustrates a cross-sectional view of a general split gate cell structure. Referring to FIG. 1, the split gate (type) cell structure includes an oxide-nitride-oxide (ONO) layer 20, a first conductive layer 30, being the floating gate, and an insulating layer (i.e., a nitride layer) 40 sequentially deposited on a semiconductor layer 10. An oxide layer 50 is formed on each side wall of the first conductive layer 30. A second conductive layer 60, being the control gate, is formed to cover only one side of the first conductive layer 30.
FIG. 2 illustrates a cross-sectional view of a control gate etching process in the related art method for fabricating a split gate flash memory. Referring to FIG. 2, a first conductive layer 20, a nitride layer 40, and an oxide layer 50 are formed. Then, a second conductive layer 60 is formed on the entire surface thereof. Subsequently, a photoresist layer 70 is deposited on the entire surface of the second conductive layer 60. After treating the photoresist layer 70 with a photolithography process and an etching process, a portion of the second conductive layer 60 remains, so as to form the control gate. The etching process of the second conductive layer is completed by removing the photoresist layer 70.
As described above, a split gate having a horizontally symmetrical structure is formed in a memory cell area. Herein, when depositing the second conductive layer 60 for forming the control gate pattern, the floating gate pattern, i.e., a deposition of the first conductive layer 30, the insulating layer 40, and the oxide layer 50, is already formed on the substrate. Therefore, step differences between the first conductive layer 30, the insulating layer 40, and the oxide layer 50 are formed, thereby causing a hollow groove (or depression) to be formed in the space between the two split gate areas, as shown in the dotted line of FIG. 2.
At this point, a photoresist layer 70 is deposited on the second conductive layer 60, and the photoresist layer 70 is treated with a light exposure process and a development process. Then, due to the above-described step difference, photoresist scum (Ps) may remain in the hollow groove portion (or depression area) of the second conductive layer 60. In addition, after forming the photoresist 70 pattern, a native oxide layer may be formed on the surface of the second conductive layer 60 in the portion having the photoresist layer 70 removed. Therefore, during a following control gate etching process, a reaction between the photoresist scum and the native oxide layer disturbs the etching process, thereby producing a polymer residue (Pr), which is a non-etched residue, in the space between the two split gate areas. However, the above-described space between the two split gate areas is a common drain area, which may cause deficiency in forming a silicide layer when the residue remains in this specific area, thereby increasing contact resistance, which in turn deteriorates the electrical characteristic of the device.